1. Field of the Invention
The present invention relates to a method of fabricating a memory device. More particularly, the present invention relates to a non-volatile memory structure and a method of fabricating a non-volatile memory.
2. Description of the Related Art
Non-volatile memory is a type of writable and erasable data that can be retained even after power to the device is cut off. In addition, non-volatile memory occupies a small volume and has a fast accessing speed with low power consumption. Moreover, since the data can be erased in a block-by-block mode, the operating speed is fast. Therefore, non-volatile memory has become one of the most popular memory devices in personal computers and other electronic equipment.
A typical non-volatile memory comprises a plurality of memory cells. Each memory cell has a tunneling layer, a floating gate, an inter-gate dielectric layer and a control gate layer sequentially stacked over each other. In general, the larger the gate coupling ratio (GCR) between the control gate layer and the floating gate layer, the lower the operating voltage needed to operate the memory. Consequently, manufacturers are striving hard to increase the capacitance of the inter-gate dielectric layer so that the gate coupling ratio can be increased. One way of increasing the capacitance of the inter-gate dielectric layer is to increase the overlapping area between the control gate layer and the floating gate layer. However, as the level of integration continues to increase, line width of the devices is getting smaller. Since there is very little space for increasing the overlapping area between the control gate layer and the floating gate layer, the performance of the memory device is ultimately affected.